1. Field of the Invention
The present invention relates to liquid crystal display devices. More particularly it relates to an array substrate for the liquid crystal display device implementing transparent pixel electrodes, data lines, and source and drain electrodes.
2. Discussion of the Related Art
A liquid crystal display device uses the optical anisotropy and polarization properties of liquid crystal molecules to produce an image. Liquid crystal molecules have a definite alignment orientation due to their long, thin shapes. The alignment orientation can be controlled by application of an electric field. Accordingly, the alignment of the liquid crystal molecules can be altered by changing the applied electric field. Due to the optical anisotropy of the liquid crystal molecules, refraction of incident light is dependent upon the orientation of the aligned liquid crystal molecules. Therefore, by controlling the electric field applied to the liquid crystal molecules, an image can be produced by the liquid crystal display device.
Liquid crystal display (LCD) devices have wide application in office automation (OA) and video equipment because of their light weight, thin design, and low power consumption characteristics. Among the different types of LCD devices, active matrix LCDs (AM-LCDs), which have thin film transistors and pixel electrodes arranged in a matrix form, offer high resolution and superiority in displaying moving images. A typical LCD panel has an upper substrate, a lower substrate and a liquid crystal material layer interposed therebetween. The upper substrate, commonly referred to as a color filter substrate, includes a common electrode and color filters. The lower substrate, commonly referred to as an array substrate, includes switching elements, such as thin film transistors (TFT's), and pixel electrodes, for example.
As previously described, operation of an LCD device is based on the principle that the alignment direction of the liquid crystal molecules is dependent upon an applied electric field between the common electrode and the pixel electrode. Accordingly, the liquid crystal molecules function as an optical modulation element having variable optical characteristics that depend upon polarity of the applied voltage.
FIG. 1 shows an LCD device according to the related art. In FIG. 1, the LCD device 11 includes an upper substrate 5, commonly referred to as a color filter substrate, and a lower substrate 22, commonly referred to as an array substrate, with a liquid crystal material layer 14 interposed therebetween. Within the upper substrate 5 and upon a surface that opposes the lower substrate 22, a black matrix 6 and a color filter layer 8 are formed in a shape of an array matrix and include a plurality of red (R), green (G), and blue (B) color filters surrounded by corresponding portions of the black matrix 6. Additionally, a common electrode 18 is formed on the upper substrate 5 to cover the color filter layer 8 and the black matrix 6. In the lower substrate 22 and upon a surface that opposes the upper substrate 5, a plurality of thin film transistors (TFT's) “T” are formed in a shape of an array matrix corresponding to the color filter layer 8. A plurality of crossing gate lines 25 and data lines 27 are positioned such that each TFT “T” is located adjacent to each intersection of the gate lines 25 and the data lines 27. Furthermore, a plurality of pixel electrodes 17 are formed on a pixel region “P” defined by the gate lines 25 and the data lines 27 of the lower substrate 22. The pixel electrode 17 includes a transparent conductive material having good transmissivity, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), for example.
In FIG. 1, a scanning signal is applied to a gate electrode of the TFT “T” through the gate line 25, and a data signal is applied to a source electrode of the TFT “T” through the data line 27. As a result, the liquid crystal molecules of the liquid crystal material layer 14 are aligned and arranged by operation of the TFT “T,” and incident light passing through the liquid crystal layer 14 is controlled to display an image. However, since the pixel and common electrodes 17 and 18 are positioned on the upper and lower substrates 5 and 22, respectively, the electric field induced between the upper and lower substrates 5 and 22 is perpendicular to opposing surfaces of the upper and lower substrates 5 and 22. The liquid crystal display device has a high transmittance and a high aperture ratio, and because the common electrode 18 on the upper substrate 5 acts as a ground, the liquid crystal is shielded from static electricity.
FIG. 2 is a partial plan view illustrating a pixel of an array substrate according to the related art. In FIG. 2, an array substrate 22 includes a thin film transistor (TFT) “T” and a pixel electrode 17 at each pixel region “P” defined by a pair of orthogonal gate lines 25 and data lines 27. The TFT “T” is arranged at one corner of the pixel region “P” and includes a gate electrode 32, a source electrode 33, a drain electrode 35, and a semiconductor layer 34. The gate electrode 32 is formed within the gate line 25 near the intersection of the gate line 25 and data line 27. The source electrode 33 extends transversely from the data line 27 over the portion of the gate line 25. The drain electrode 35 extends from the pixel electrode 17 arranged in the pixel region “P,” and is spaced apart from the source electrode 33 to form a channel region on the semiconductor layer 34.
The data line 27, the source electrode 34, the drain electrode 35 and the pixel electrode 17 are made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), for example. However, since the transparent conductive material has a relatively high electrical resistance as compared to other metallic materials, the data line 27 formed of the transparent conductive material increases signal delay, thereby degrading the reliability of the LCD device. Accordingly, to decrease the electrical resistance in the data line 27, an additional metal 28 having a low electrical resistance is formed at an edge portion of the data line 27 using electroplating of a metallic coating.
FIGS. 3A to 3F are cross-sectional views taken along III-III of FIG. 2, and show fabricating processes of an array substrate having the transparent data line and source electrode according to the related art.
In FIG. 3A, a substrate 22 may be cleaned of organic materials and any foreign substances to promote adhesion with a first metal layer that may be subsequently deposited on the substrate 22 by a sputtering process, for example. The first metal layer is a metallic material, such as aluminum or aluminum neodymium (AlNd), for example. The first metal layer is subsequently patterned using a first mask to form a gate line 25 (of FIG. 2) in a transverse direction, and a gate electrode 32 that is a portion of the gate line 25. Alternatively, a double-layered structure may be used for the gate line 25 and the gate electrode 32. The double-layered structure includes an aluminum (Al) layer stacked with a molybdenum (Mo) layer or a chromium (Cr) layer, for example, that has high corrosion resistance and durability. Then, a gate insulation layer 41 is formed on a surface of the substrate 22 to cover the patterned first metal layer. The gate insulation layer 41 may include silicon oxide (SiOX) or silicon nitride (SiNX). A pure amorphous silicon (a-Si:H) layer 45a and a doped amorphous silicon (n+ a-Si:H) layer 47a are sequentially formed upon the gate insulation layer 41.
FIG. 3B shows a step of forming an active layer and an ohmic contact layer. In FIG. 3B, the pure amorphous silicon layer 45a and the doped amorphous silicon layer 47a are simultaneously patterned using a second mask to form an active layer 45b, and an ohmic contact layer 47b upon the gate insulation layer 41, respectively. Alternatively, the pure amorphous silicon layer 45a and the doped amorphous silicon layer 47a can be patterned by rear exposure using the patterned first metal as a mask, such that the active layer 45b and the ohmic contact layer 47b can be formed over the patterned first metal layer (i.e., over the gate line 25 of FIG. 2).
FIG. 3C shows a step of forming a data line, a source electrode, a drain electrode and a pixel electrode. In FIG. 3C, a transparent conductive material 50, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is formed upon an entire surface of the gate insulation layer 41, thereby covering the active layer 45b and ohmic contact layer 47b. Thereafter, a photoresist layer 52 is formed on the transparent conductive material 50, and then a third mask 54 is aligned over the photoresist layer 52.
FIG. 3D shows a step of forming contact portions within the photoresist layer 52. In FIG. 3D, the photoresist layer 52 is developed to expose portions of the transparent conductive material 50. Residual photoresist layer portions 52a remain over a data portion “A,” a source portion “B,” a drain portion “C,” and a pixel portion “D” of the transparent conductive material 50. Specifically, edge regions of the residual photoresist layer portions 52a are thinner than central regions thereof.
FIG. 3E shows a step of etching the residual photoresist layer portions 52a. In FIG. 3E, the residual photoresist layer portions 52a are sufficiently etched using a dry etching method, thereby removing the exposed portions of the transparent conductive material 50 (of FIG. 3D). Furthermore, the edge regions of the residual photoresist layer portions 52a are also removed to expose peripheral portions “K” of the etched transparent conductive material 50.
FIG. 3F shows a step of etching the peripheral portions “K” of the etched transparent conductive material 50. In FIG. 3F, the peripheral portions “K” of the etched transparent conductive material are plated with a second metal 28 using an electroplating process. The second metal 28 includes a low electrical resistance material such as copper (Cu) or aluminum (Al). Then, the residual photoresist layer portions 52a are completely removed from the etched transparent conductive material 50, and data lines 27, a source electrode 33, a drain electrode 35, and pixel electrodes 17 are formed on the substrate 22. The source electrode 33 extends from the data line 27, and the drain electrode 35 extends from the pixel electrode 17. The source and drain electrodes 33 and 35 are spaced apart from each other and overlap opposite ends of the gate electrode 32. Accordingly, the thin film transistor “T” includes the gate electrode 32, the semiconductor layer 34, and the source and drain electrode 33 and 35.
However, the data line 27, which includes the second metal 28 formed at peripheral regions thereof is problematic. Specifically, since the second metal 28 formed on the data line 27 is so small, the data line 27 has a relatively high electrical resistance. As a result, it is very difficult to steadily apply signals through the data line 27.